Synthesis of multiple-valued logic networks for FPGA implementation using developmental genetic programming

This paper presents a method of FPGA-oriented synthesis of multiple-valued logical networks. A multiple-valued network consists of modules connected by multivalued signals. During synthesis the modules are decomposed into smaller ones. For this purpose the symbolic decomposition is applied. Since the decomposition of modules strongly depends on the encoding of multiple-valued inputs and outputs, the result of synthesis depends on the order, in which the consecutive modules are implemented. Experimental results showed that our approach significantly reduces the cost of implementation.